In this paper, a LC voltage-controlled oscillator (LC-VCO) design optimization methodology based on switchable capacitor array is presented. The study of the compromises between phase noise and tuning range permits optimization of the design for given specifications. According to analytical phase noise models and tuning range, it allow to get a design space map where the design tradeoffs are easily identified. The proposed VCO is designed with the proposed methodology and implemented in SMIC's 0.18-μm RF CMOS technology and the chip area is 650 μm × 500 μm, including the test buffer circuit and the pads. Simulation results show that its tuning range is 36.4%, from 4.5 to 6.5 GHz. The simulating phase noise is -112.8 dBc/Hz at 1 MHz offset from the 6.5 GHz carrier. The maximum average power consumption of the core part is 6.47 mW at 1.8 V power supply.
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