Multi-core Processor Simulation Vector Learning Optimization Based on S~2LS-SVM

摘要

With the revolutionary progress of the EDA industry, the verification of microprocessor becomes more and more difficult. It is a big problem to optimize the huge verification stimuli. Verification stimuli efficiency problem is researched in our paper and multi-core processor verification vector learning method based on S~2LS-SVM is put forward. First, verification stimuli are generated according to coverage information, the simulation vectors feature selection and extraction is conducted by transition probability matrix. Initial S~2LS-SVM classifier is trained on the labeled training set, area labeling principle is used for unlabeled samples tagging, dynamic adjustment of centralized "inconsistent" semi-labeled samples; then, train a classifier with the label sample and semi-labeled samples, classifier predict the new stimuli vector is a redundancy or not, if it is redundant, it will not need to do the simulation. Effective label sample provides SMT Solver feedback to the classifier for incremental updates. Experimental results show that this method of training is fast, the simulation vectors can be reduced significantly and rapid verification closure is achieved. It also has important reference value for the future multi-core processors simulation.