Cost efficient realization synthesis of reversible presettable program counter for processor

摘要

A counter is a register capable of counting number of clock pulses that is being needed for its operation. In its simplest form its equivalent to a binary odometer. As reversible logic is considered to be the best effective way to enhance the energy efficiency than the conventional models we should drive ourselves to have a counter in reversible logic. In this paper, we have demonstrated a novel reversible N-bit pre-settable counter circuit which can also be used as program counter of microprocessor. While approaching for the same, we have designed a new cost efficient reversible JK Flip-flop with asynchronous inputs followed by reversible ripple & synchronous counter and analyzed their operation, delay, quantum cost & garbage in terms of some algorithms and lemmas, which will outperform the existing designs available in literature.