A two-gap capacitive structure for high aspect-ratio capacitive sensor arrays

机译：用于高纵横比电容传感器阵列的两间隙电容结构

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This paper presents a two-gap CMOS-compatible technology to fabricate very tall (>500¿¿m) 3D high aspect-ratio (HAR) silicon structures with narrow HAR sensing gaps (

机译：本文提出了一种两间隙CMOS兼容技术，以制造具有狭窄HAR感应间隙的非常高（>500μm）3D高纵横比（HAR）硅结构（

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《IEEE International Electron Devices Meeting》|2015年|1-4|共4页
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Yemin Tang; Khalil Najafi;
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DRIE; accelerometer; air gap; array; bonding; capacitive sensor; high aspect ratio;

机译：DRIE;加速度计;气隙;阵列;键合;电容传感器;高纵横比;

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A two-gap capacitive structure for high aspect-ratio capacitive sensor arrays

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