The combination of multiple-input multiple-output (MIMO) and Space-Time Block Coding (STBC) is a potential solution for increasing throughput and reliability in data transmission. A pipelined architecture for a Schnorr-Euchner algorithm based sphere decoder used in STBC systems is proposed in this paper. The architecture was designed for a 2×2 antenna system with 16-quadrature amplitude modulation (16-QAM). The architecture was synthesized and implemented on a Xilinx Virtex-7 FPGA. The implementation results have shown that the proposed architecture outperforms existing ones in terms of throughput and maximum clock frequency thanks to pipelined processing.
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