Temperature-Aware Register Mapping in GPGPUs

摘要

Various architectural-based techniques have been proposed to reduce power consumption in GPGPUs. However, these techniques mostly ignore temperature of GPGPUs. In this paper, we focus on the register file and propose a new technique to reduce its peak temperature. Register file in GPGPUs is very large, even larger than caches, to support thousands of simultaneously execution threads. This makes register file a power-hungry component in GPGPUs and increases its heat dissipation. We propose Distant wArp Register maPping (DARP) to maximize distance between warp registers. By maximizing distance between consecutively accessed regions of the register file, we minimize the hotspots in the register file, and hence reduce the peak temperature. Furthermore, we power gate unallocated registers and reduce voltage of idle registers to reduce leakage power and so the temperature further. To overcome performance penalty of voltage scaling, we change voltage of registers in granularity of regions and reduce the number of state switching in register file. Overall, our optimization techniques reduce peak temperature by 5.02°C with negligible impact on performance.