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An Energy-Efficient and Scalable eDRAM-Based Register File Architecture for GPGPU

机译：用于GpGpU的节能且可扩展的基于eDRam的寄存器文件架构

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Naifeng Jing; Yao Shen; Yao Lu; Shrikanth Ganapathy; Zhigang Mao; Minyi Guo; Ramon Canal; Xiaoyao Liang;
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年度 2016
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1. An Energy-Efficient and Scalable eDRAM-Based Register File Architecture for GPGPU [J] . Naifeng Jing, Yao Shen, Yao Lu, Computer architecture news . 2013,第3期

机译：GPGPU的节能，可扩展，基于eDRAM的寄存器文件架构
2. Energy-Efficient eDRAM-Based On-Chip Storage Architecture for GPGPUs [J] . Jing Naifeng, Jiang Li, Zhang Tao, Computers, IEEE Transactions on . 2016,第1期

机译：基于节能的基于eDRAM的GPGPU片上存储架构
3. An Energy-Efficient GPGPU Register File Architecture Using Racetrack Memory [J] . Mengjie Mao, Wujie Wen, Yaojun Zhang, IEEE Transactions on Computers . 2017,第9期

机译：使用Racetrack内存的节能GPGPU寄存器文件架构
4. LAD-ECC: Energy-Efficient ECC Mechanism for GPGPUs Register File [C] . Xiaohui Wei, Hengshan Yue, Jingweijia Tan Design, Automation and Test in Europe Conference and Exhibition . 2020

机译：LAD-ECC：GPGPU寄存器文件的节能ECC机制
5. An efficient architecture for detection of multiple bit upsets in processor register files. [D] . Yueh, Wen. 2009

机译：一种用于检测处理器寄存器文件中多个位翻转的有效架构。
6. Optimizing Instruction Scheduling and Register Allocation for Register-File-Connected Clustered VLIW Architectures [O] . Haijing Tang, Xu Yang, Siye Wang, 2013

机译：连接寄存器文件的集群式VLIW架构的优化指令调度和寄存器分配
7. Hybrid CMOS-TFET based Register Files for Energy-Efficient GPGPUs [O] . Zhi Li, Jingweijia Tan, Xin Fu 2013

机译：用于节能GpGpU的基于混合CmOs-TFET的寄存器文件

An Energy-Efficient and Scalable eDRAM-Based Register File Architecture for GPGPU

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