CMOS digital integrated circuits; oscillators; time-digital conversion; time-domain analysis; CMOS process; Nyquist input; RO; TDC; area-efficient time-domain conversion technique; back-end complexity; built-in dynamic element matching feature; clock-skew calibration; front-end single-VTC; front-end single-voltage-to-time converter; inherent DEM; inherent folding effect; ring oscillator; silicon area; size 65 nm; time-domain folding ADC; time-interleaved ADC; time-to-digital converter; word length 6 bit; Clocks; Delays; Discharges (electric); Partial discharges; Quantization (signal); Time-domain analysis; folding ADC; time amplifier; time domain; time-to-digital converter; voltage-to-time converter;
机译:一个用于65nm CMOS的时间交错SAR ADC的10GS / s 6位采样保持放大器
机译:65nm CMOS 6位2.5-GS / s 7.5mW 8
机译:具有紧凑型时域信号折叠和固有DEM的无歪斜10 GS / s 6位CMOS ADC
机译:具有固有DEM的65-NM CMOS中的0.073mm 2 sup> 10-gs / s 6位时域折叠adc
机译:时域模数转换和GigaHertz时域折叠/闪存ADC
机译:使用亚微米CMOS技术设计高速,6位管线ADC,内置数字误差校正单元。