Implementation of floating point fused basic arithmetic module using Verilog

摘要

This paper describes basic arithmetic module using Verilog operations and applies them to the implementation of fast Fourier transform (FFT) processors. The fused operations of like addition subtraction unit. Which can be used for DSP are implementation efficiently with the two fused floating-point operations. When placed and routed using a high performance standard cell technology like vertex -5, the fused arithmetic modules are efficiently works fast and gives user defined facility to modify the butterfly's structure. Also the numerical results of the fused implementations are more accurate, as they use rounding modes is defined as per user requirement. All modules are implemented by using Verilog HDL.