17-MS/s 9-bit cyclic ADC with gain-assisted MDAC and attenuation-based calibration

摘要

A 17-MS/s 52.5-dB-SNDR 4.7-mW 0.045-mm cyclic ADC has been achieved by the low-cost 0.18-μm CMOS. The only-26-dB gain of a simple op-amp has been successfully compensated by the proposed gain-assisted MDAC circuit and by the novel simple attenuation-based digital calibration. The prototype ADC chip has achieved the fastest speed, the smallest size and the best FOM among the high-speed (> 5 MS/s) highresolution (SNDR > 50 dB) low-cost-CMOS cyclic ADCs.