MOSFET; SRAM chips; electric breakdown; hot carriers; integrated circuit design; integrated circuit reliability; logic design; low-power electronics; SRAM architecture; SRAM bit cell; SRAM designs; TDDB; TSMC FinFET technology; VDDMIN environment; bit cell write margin; gate oxide tox reliability; hot carrier injection; overdrive word line write assist circuits; power supply rail; size 16 nm; time-dependent dielectric breakdown; voltage 0.52 V; voltage 85 mV; word line voltage level; write ability; write scheme; Circuit stability; Computer architecture; Delays; Logic gates; Microprocessors; Multiplexing; Random access memory; Psuedo read; Register files; SNM improvement; SRAM; VDDMIN improvement; Write cycle; Write margin improvement;
机译:使用单层和双层过渡金属双硫属金属化物(TMD)MOSFET的随机变化对低压SRAM的单元稳定性和写入能力的影响
机译:一个28 nm 2 Mbit 6 T SRAM,具有高度可配置的低压写能力辅助实现和基于电容器的感测放大器输入失调补偿
机译:利用瞬态负位线电压改善SRAM的写入能力
机译:两相写方案,以提高中密度SRAM中的低压写入能力
机译:纳米级SRAM的电源电压最小化和良率感知。
机译:低压电网中降低电压不平衡的协调单相控制方案
机译:字线电压加速对SRAM单元写裕度的改进评估方法