VLSI; buffer circuits; clocks; estimation theory; integrated circuit design; integrated circuit testing; network routing; BBLUE; IBM; ISPD 2010 benchmark; Intel; Steiner point insertion; VLSI circuit design; blockage look up and buffer estimation; buffer insertion; physical design constraint; rectilinear steiner clock tree routing design technique; skew minimization; Benchmark testing; Clocks; Delays; Minimization; Routing; Synchronization; Wires; Buffer Insertion; Clock Tree; Obstacle Avoiding Rectilinear Steiner Tree; Skew Minimization; VLSI Routing;
机译:基于临界干线的障碍避免直线斯坦纳树路由和缓冲区插入,以实现延迟和松弛优化
机译:ObSteiner:存在复杂直线障碍物时构造直线Steiner最小树的精确算法
机译:基于迷宫路由的方法,具有限制多层障碍避免直线施坦纳结构的受限制勘探和路径评估的回溯
机译:直线施泰纳时钟路线路线技术,缓冲区插入存在障碍物
机译:关于障碍中直线型斯坦纳最小树的构造
机译:一种有效的路由树构造算法,具有缓冲区插入,线缆尺寸和障碍考虑
机译:用于直线steiner树问题的工具