首页> 外文会议>IEEE China Summit International Conference on Signal and Information Processing >A high-efficiency loop delay estimator in digital predistortion subsystem
【24h】

A high-efficiency loop delay estimator in digital predistortion subsystem

机译:数字预失真子系统中的高效环路延迟估计器

获取原文

摘要

A high-efficiency time delay estimation method is presented to obtain the accurate loop delay (including integer and fractional loop delay) between the input signal and the time delayed feedback signal in digital predistortion subsystem within the same process. Compared with the conventional, a sampling position adjusting scheme for complex signals using the piecewise-parabolic filter assisted by a steady decision criterion for limited data length achieves a significant reduction in time complexity and an improvement in loop delay estimation stability and precision. Results from simulations and experiments show that the proposed method is high-efficiency and valid.
机译:提出了一种高效率的时间延迟估计方法,以在同一过程内的数字预失真子系统中的输入信号和时间延迟反馈信号之间获得精确的循环延迟(包括整数和分数循环延迟)。与传统的传统相比,使用由稳定的判定标准辅助的分段 - 抛物滤波器用于有限数据长度辅助的复杂信号的采样位置调整方案实现了对时间复杂性的显着降低和环路延迟估计稳定性和精度的提高。模拟和实验结果表明,该方法是高效率和有效的。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号