首页> 外国专利> JOINT PROCESS ESTIMATOR WITH VARIABLE TAP DELAY LINE FOR USE IN POWER AMPLIFIER DIGITAL PREDISTORTION

JOINT PROCESS ESTIMATOR WITH VARIABLE TAP DELAY LINE FOR USE IN POWER AMPLIFIER DIGITAL PREDISTORTION

机译:具有可变TAP延迟线的联合过程估计器,用于功率放大器数字预失真

摘要

Methods and circuits for pre-distorting a signal to compensate for distortion introduced by an electronic device operating on the signal. In an example method, first and second signal samples representing the input and output of the electronic device are generated. The first and second signal samples are spaced at unit-delay intervals, and each of the second signal samples corresponds in time to one of the first signal samples. Pre-distortion weights are then calculated from the first and second signal samples, the pre-distortion weights corresponding to a pre-distortion model comprising a lattice-predictor memory model structure having multiple delays and having at least one multi-unit delay interval between adjacent delays. The calculated pre-distortion weights are then applied to the input signal, using a predistorter with a structure corresponding to the lattice-predictor memory model, to produce a pre-distorted input signal for input to the electronic device.
机译:用于预失真信号以补偿由对信号进行操作的电子设备引入的失真的方法和电路。在示例方法中,生成表示电子设备的输入和输出的第一和第二信号样本。第一和第二信号样本以单位延迟间隔间隔开,并且每个第二信号样本在时间上对应于第一信号样本中的一个。然后从第一和第二信号样本中计算出预失真权重,该预失真权重对应于预失真模型,该预失真模型包括具有多个延迟并且在相邻之间具有至少一个多单元延迟间隔的晶格预测器存储器模型结构。延误。然后,使用具有与格状预测器存储器模型相对应的结构的预失真器,将计算出的预失真权重应用于输入信号,以产生预失真的输入信号,以输入至电子设备。

著录项

  • 公开/公告号EP2641324B1

    专利类型

  • 公开/公告日2014-08-20

    原文格式PDF

  • 申请/专利权人 ERICSSON TELEFON AB L M;

    申请/专利号EP20100795048

  • 发明设计人 KILAMBI SAI;LEHMAN BRIAN;BAI CHUNLONG;

    申请日2010-11-16

  • 分类号H03F3/195;H03F3/24;H03F1/32;

  • 国家 EP

  • 入库时间 2022-08-21 15:48:20

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