Sparsity-aware model reduction for post-layout circuit simulation

摘要

Post-layout simulation becomes more and more challenging due to ever increasing parasitics. Reducing the order of systems does not necessarily result in improvement in simulation time. What really affects the simulation time is the network complexity, which is determined by both the size and density of the network. Only reducing the size may worsen the density and in turn the complexity of the “reduced” system may be even higher compared with the original systems. We thus proposed a model complexity reduction which comprises sparsity-aware model reduction followed by model sparsification. Experiments show that for realistic post-layout simulation problems, the proposed model complexity reduction provides 3X~5X speed-ups compared with simulation using the original circuits.