A 14b continuous-time delta-sigma modulator with 2MHz signal bandwidth

摘要

A 14-bit 10mW 2MHz BW continuous-time (CT) ΔΣ modulator, implemented in UMC 180nm process, is presented in this paper. High-speed high-resolution low-noise dynamic latch comparator is designed for quantization. A low-latency dynamic element matching (DEM) module is included in consideration of nonlinear mismatching of DAC units. R introduces direct feedforward path around the quantizer to compensate for excess loop delay (ELD), which is more efficient in power and area compared to conventional structure. The post-layout simulation achieves a SNDR of 79dB with a FOM of 350fJ/conv-step and occupies 0.1mm active area.