首页> 外文会议>IEEE International Electron Devices Meeting >High-performance CMOS-compatible self-aligned In0.53Ga0.47As MOSFETs with GMSAT over 2200 µS/µm at VDD = 0.5 V
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High-performance CMOS-compatible self-aligned In0.53Ga0.47As MOSFETs with GMSAT over 2200 µS/µm at VDD = 0.5 V

机译:高性能CMOS兼容自对准In 0.53 Ga 0.47 As MOSFET,GMSAT在V DD = 0.5 V时超过2200 µS / µm

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摘要

We demonstrate high-performance self-aligned InGaAs-channel MOSFETs with effective channel length L down to 20 nm, peak transconductance G over 2200 μS/μm at L = 30 nm and supply voltage V = 0.5 V, thin inversion oxide thickness T = 1.8 nm, and low series resistance R = 270 Ω.μm. These MOSFETs operate within 20% of the ballistic limit for L ≤ 30 nm and are among the best InGaAs FETs in literature. We investigate the effects of channel/barrier doping on FET performance and show that increase in mobility beyond ~ 500 cm/Vs has progressively smaller impact as L is scaled down. Our self-aligned MOSFETs were fabricated using a CMOS-compatible process flow that includes gate and spacer formation using RIE, source/drain extension (SDE) implantation, and in-situ-doped raised source/drain (RSD) epitaxy. This process flow is manufacturable and easily extendable to non-planar architectures.
机译:我们展示了一种高性能的自对准InGaAs沟道MOSFET,其有效沟道长度L低至20 nm,在L = 30 nm时峰值跨导G超过2200μS/μm,电源电压V = 0.5 V,薄的反型氧化物厚度T = 1.8 nm,低串联电阻R = 270Ω.m。这些MOSFET在L≤30 nm的防弹极限的20%范围内运行,并且是文献中最好的InGaAs FET之一。我们研究了沟道/势垒掺杂对FET性能的影响,结果表明,随着L的减小,超过500 cm / Vs的迁移率增加产生的影响逐渐减小。我们的自对准MOSFET是使用CMOS兼容工艺流程制造的,该流程包括使用RIE形成栅极和隔离层,源极/漏极扩展(SDE)注入以及原位掺杂凸起的源极/漏极(RSD)外延。该工艺流程是可制造的,并且很容易扩展到非平面架构。

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