CMOS digital integrated circuits; circuit optimisation; low-power electronics; power consumption; timing; CMOS digital flow; circuit power consumption; delays scale; digital standard cell libraries; dual-Vlt; subgt; thlt; /subgt; devices; microcontroller core; multiple threshold voltages; optimization; size 65 nm; supply voltage scaling; timing analysis; timing errors; voltage scaled CMOS digital circuits; word length 8 bit; Delays; Libraries; Logic gates; Mathematical model; Ring oscillators; Standards;
机译:倾斜沉积的[Pb(Mg
机译:依赖温度宽带电介质,磁性和电气研究Li
机译:开路电压对Ni-Al微放电加工的影响
机译:采用双V
机译:结合可变电源电压和自适应主体偏置的CMOS电路的分析,优化和建模。
机译:为低压可穿戴传感器应用而优化的超薄印刷有机TFT CMOS逻辑电路的制造
机译:基于P型GE