A 2-clock-cycle Na?ve Bayes classifier for dynamic branch prediction in pipelined RISC microprocessors

摘要

In this paper, we propose a Bayesian branch-prediction circuit consisting of an instruction-feature extractor and a nai?ve Bayes classifier (NBC). Its purpose is to replace conventional branch predictors in modern pipelined RISC microprocessors. The proposed circuit is based on the conventional neural branch predictor [1]; however, the linear classifier circuit is replaced by the proposed NBC circuit. Implementing approximate Bayesian computation and its highly-parallel architectures, the NBC circuit completes branch prediction within 2 clock cycles per instruction, and is this suitable for implementation on standard pipelined microprocessors.