Efficient VLSI Design for RNS Reverse Converter Based on New Moduli Set (2{sup}n-1, 2{sup}n+1, 2{sup}(2n+1))

摘要

In this paper we present a new 3-moduli set (2{sup}n-1, 2{sup}n+1, 2{sup}(2n+1)) and its RNS reverse converter design. The proposed 3-moduli set supports 1) larger dynamic range and 2) shorter internal computing delay, comparing to the most popular modular set (2{sup}n-1, 2{sup}n+1, 2{sup}n). Besides, to speed up residue to binary conversion, a low-cost hardware circuit is designed by only using two carry-save adders and one end around carry CLA (EACLA). Under the same dynamic range requirement, our proposed converter design is significantly more efficient than the latest design for modular set (2{sup}n-1, 2{sup}n+1, 2{sup}n) with respect to hardware cost and Area-Time product (AT). Based on UMC 0.18μm CMOS cell-based technology, the core area for 16-bit RNS reverse converter is only 1836μm{sup}2 and the working frequency is 388MHz.