Skew tolerance analysis and layout design of 4×4 multiplier using two phase clocking subthreshold adiabatic logic

摘要

We have previously proposed a new digital CMOS circuit which combined subthreshold circuit and adiabatic logic circuit with ultra-low power consumption. Our proposed circuit which is driven by two AC power supply with different frequency and amplitude, and is adapted to be provided a margin of switching timing of input signal. In this paper, we show a skew tolerance analysis of subthreshold adiabatic logic circuit. From skew analysis, we see that the proposed circuit correctly operates. Circuit operation and performance is evaluated using a 4×4-bit multiplier fabricated in a 0.18 μm CMOS process. The post layout results show that the multiplier was operated with clock frequencies 1 kHz.