Efficient diminished-1 modulo 2n#x002B;1 multiplier architectures

摘要

The main components of an artificial neuron are adders and multipliers. In order to implement neural network, large number of adders and multipliers are required. The efficient architectures for diminished-1 modulo 2n+1 multipliers are described. The results and operands of the new modulo 2n+1 multipliers use the diminished-1, avoiding n+1 bit circuit. And the presented multipliers can handle zero inputs and results. The proposed modulo 2n +l multiplier are built using three major functional modules, partial products generation block, partial products reduction block and a final diminished-1 adder block. The final modulo 2n +l addition block is built around a sparse carry computation unit for the analytical and experimental results. And this indicates that the significant area and power of the proposed multipliers is superior to the earlier proposals, with a high operation speed.