Reduced Precision Redundancy (RPR) is demonstrated as a new method for improving fault tolerance in Field Programmable Gate Arrays (FPGAs) replacing Triple Modular Redundancy (TMR) to protect against the Single Event Effects due to radiation in arithmetic processes. As a test of this approach, the RPR technique was used to implement a Radix-4 Fast Fourier Transform (FFT). This design was implemented in a Xilinx Virtex 2~(~R) FPGA in order to find the possible gain in speed and reduction in power and resources as compared to the TMR method. Simulation of different degrees of RPR explore the impact on speed and power on the FPGA performance at various levels of precision reduction. This paper deals with a 64-point 32-bit 3-stage Radix-4 in-place FFT based on an improved FFT algorithm. The whole FFT structure was implemented based on modules designed by the author and Virtex 2~(~R) FPGA's modules. The implementation of the FFT was successful and was able to handle data in real time at a throughput rate (sample rate) of 134 MHz in simulation. Based on this FFT design, the implementation of TMR and RPR modules was attempted. First, the TMR structure was designed, creating three identical replicas of the FFT and installing a TMR Voter per FFT's stage. The implementation of this design was not possible due to resource requirements just exceeding the capabilities of the FPGA. The next step was the alteration of the existing FFT and the creation of a smaller 14-bit Butterfly module (BF) for the bound-computing portion of the RPR structure. After the successful completion of this step, we advanced to the implementation of an RPR module with a 14-bit reduced precision bound and a 32-bit precise value (RPR degree 14/32). This design employed a new approach to RPR where two copies of the truncated lower bound are computed separately from the precise value. The degree 14/32 RPR, Radix-4, 3-stage pipeline FFT functioned correctly and was able to work in real time handling data at a throughput of 163 MHz.
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