Using TBD and Iwearout characterization and modeling, the influence of antifuse bitcell dimensions is evaluated. An analytical model based on silicon measurements and reliability laws allows the comparison of three bitcell architectures fabricated in standard CMOS 40nm (no extra processing). The model yields the time-to-breakdown and the wearout current as a function of the programming voltage and the dimensions of the antifuse bitcell. As a main result, it is demonstrated that a device with a small capacitor area exhibits shorter TBD, lower Iwearout, and hence a lower programming energy. Characterization and modeling are performed for a programming voltage range from 3.5V to 7V with a minimum TBD of 9ns.
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