A 105dBA SNR, 0.0031 THD+N filterless class-D amplifier with discrete time feedback control in 55nm CMOS

摘要

It is traditionally difficult to implement higher order PWM closed loop class-D audio amplifiers using analog techniques. This paper describes a mixed signal approach, implementing a 4 order amplifier in 55nm CMOS with minimal demands on a front-end ADC. An approach to design the feedback loop in the digital domain with high gain throughout the audio band (100dB at DC) to improve linearity and PSRR is also outlined. The prototype achieves 105dBA SNR, 0.0031% THD+N, 92dB PSRR and 85% efficiency when supplying 1W into emulated 8Q microphone load. This performance represents an improvement over reported designs in advanced nodes and is competitive with conventional designs using large feature size precision CMOS or specialized BCD technologies.