A 500nA quiescent current, trim-free, ±1.75 absolute accuracy, CMOS-only voltage reference based on anti-doped N-channel MOSFETs

摘要

In this paper, an ultra low power CMOS-only voltage reference is presented. The reference exploits the work function difference between anti-doped (flipped-gate) and standard-doped nMOS devices. These devices require no additional processing and are realizable from the basic N+ and P+ implants used to implement the standard enhancement mode MOS devices on the process. The reference is implemented as a temperature-compensated ΔV between anti-doped and standard-doped nMOS devices. Integrated on 0.18μm CMOS, the reference occupies less than 0.04mm on silicon, requires less than 500nA of quiescent current, and has a trim-free accuracy of ±1.75% which is comparable to that of the most well-behaved voltage references employing BJTs.