A tri-stack buck converter with gate coupling control (GCC) and quasi adaptive dead time control (QADTC)

摘要

A DC-DC buck converter handling three times the nomal transistors' nominal voltage is implemented with 1.8V I/O devices in a 65nm digital process with the aim of creating an analog intellectual property that is robust, easily reconfigurable and cost effective. Moreover, the maximum current density and the efficiency of the powering block reach to 1.28A/mm and 93.8%, respectively, with the help of the high mobility of the transistor.