A 11μW 250 Hz BW two-step incremental ADC with 100 dB DR and 91 dB SNDR for integrated sensor interfaces

摘要

A two-step incremental ADC (IADC) is proposed for low-bandwidth, micro-power sensor interface circuits. This architecture extends the order of a conventional IADC from N to (2N-1) by using a two-step operation, while requiring only the circuitry of an N-order IADC. The implemented third-order IADC achieves a measured dynamic range of 99.8 dB and an SNDR of 91 dB for a maximum input 2.2 V and 250 Hz bandwidth. Fabricated in 65 nm CMOS, the IADC's core area is 0.2 mm, and consumes only 10.7 μW. The FoMs are 0.76 pJ/conversion-step and 173.5 dB, both among the best reported results.