Synthesis of asynchronous QDI circuits using synchronous coding specifications

摘要

We propose a synthesis of asynchronous quasi-delay-insensitive (QDI) circuits. We highlight three notably featuresovelties of the proposed synthesis as follows. First, the targeted synthesized circuits abide by the QDI protocol; hence they are inherently timing-robust and are desirable for applications with high variation-space and wide operation-space (including defense/space applications). Second, the coding specifications accept Verilog HDL language, and are the same/similar to the standard coding for synchronous circuits, hence no special and/or ad-hoc design/coding rules are required. Third, the proposed synthesis is applicable to accept various QDI library cells, hence enabling to explore full merit of different library cells. To the best of our knowledge, no reported synthesis methods incorporate all these features; some limited features were only incorporated. Our proposed synthesis, at this juncture, accepts three basic clauses - complete ‘if-else’ clause, incomplete ‘if-else clause’, and the ‘case’ clause. These clauses are more than sufficient to describe any complex systems. The synthesis stages involve analyzing QDI pipelines, generating (corresponding) single-rail combinational circuits, converting dual-rail netlists (from the single-rail circuits), and embedding customized controllers. In order to demonstrate the validity and practicality of the proposed synthesis, an 8-bit 8-tap asynchronous QDI Finite Impulse Response (FIR) filter is synthesized, implemented to the layout stage, and evaluated using spice models-specifically, it features 3.7 mW power dissipation, 39,181 transistors, and a delay of 200 ns per operation.