A low-power Spread Spectrum Clock Generator with an embeddable half-integer division ratio interpolator

摘要

This study proposes a Spread Spectrum Clock Generator (SSCG) for Serial-ATA II, which is realized by a delta-sigma fractional-N frequency synthesizer with a digital triangular profile generator without external clock and a half-integer divider. By adding only a negative-edge-triggered resampler and using phase combination technique, the half-integer divider can be realized by any kind of integer programmable divider with little power consumption added. This half-integer divider utilizes a half division ration to obtain a small phase jump to reduce quantization noise. The SSCG prototype, which has been produced in 0.18-µm CMOS technology, achieves an output clock of 3 GHz and 4883ppm down spread with a 30 KHz triangular waveform. The EMI reduction is 13 dB and the power consumption is as low as 12 mW under 1.8-V power supply.