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On the Fast Generation of Long-period Pseudorandom Number Sequences

机译:在快速生成长期伪随机数序列

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Monte Carlo simulations and other scientific applications that depend on random numbers are increasingly implemented in parallel configurations in programmable hardware. High-quality pseudo-random number generators (PRNGs), such as the Mersenne Twister, are based on binary linear recurrence equations. They have extremely long periods (more than 2{sup}1024 numbers generated before the entire sequence repeats) and well-proven statistical properties. Many software implementations of such 'long-period' PRNGs exist, but hardware implementations are rare. We develop optimized, resource-efficient parallel architectures for long-period PRNGs that generate multiple independent streams by exploiting the underlying algorithm as well as hardware-specific architectural features. We demonstrate the utility of the framework through parallelized implementations of three types of PRNGs on a field-programmable gate array (FPGA). The area/throughput performance is impressive: for example, compared clock-for-clock with a previous FPGA implementation, a "two-parallelized" 32-bit Mersenne Twister uses 41% fewer resources. It can also scale to 350MHz for a throughput of 22.4Gbps, which is 5.5x faster than the previous implementation and 7.1x faster than a dedicated software implementation. The quality of generated random numbers is verified with standard statistical test batteries. To complete testing, we present a real-world application study by coupling our parallel hardware RNGs to the Ziggurat algorithm for generating normal random variables. The availability of fast long-period random number generators accelerates hardware-based scientific simulations and allows them to scale to greater complexities.
机译:蒙特卡罗模拟和其他依赖于随机数的科学应用越来越多地在可编程硬件中的并行配置中实现。高质量的伪随机数发生器(PRNG),如Mersenne Twister,基于二进制线性复发方程。它们具有极长的时期(在整个序列重复之前产生的超过2 {sup} 1024号)和经过精心证明的统计属性。存在这种“长期”PRNG的软件实现,但硬件实现是罕见的。我们通过利用底层算法以及硬件特定的架构功能,为长期PRNG开发优化的,资源有效的并行架构,该架构通过利用底层算法以及硬件特定的架构功能来生成多个独立流。我们通过在现场可编程门阵列(FPGA)上的三种类型的PRNG的并行实现来展示框架的实用性。区域/吞吐量性能令人印象深刻:例如,使用以前的FPGA实现比较时钟 - 时钟,一个“双行化”32位Mersenne Twister使用41%的资源。它还可以缩放到350MHz的吞吐量为22.4Gbps,比以前的实施方式快5.5倍,比专用软件实现快7.1倍。使用标准统计测试电池验证生成的随机数的质量。为了完成测试,我们通过将我们的并联硬件RNG耦合到Ziggurat算法来产生一个真实的应用程序研究,以产生正常随机变量。快速长期随机数发生器的可用性加速了基于硬件的科学模拟,并允许它们扩展到更大的复杂性。

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