Increasing demand for higher-bandwidth DRAM drive TSV technology development. With the capacity of fine-pitch wide I/O [1], DRAM can be directly integrated on the interposer or host chip and communicate with the memory controller. However, there are many limitations, such as reliability and testability, in developing the technology. It is advantageous to adopt a logic-interface chip between the interposer and stacked-DRAM with thousands of TSV. The logic interface chip in the base level of high-bandwidth memory (HBM) decreases the CIO, repairs the chip-to-chip connection failure, and supports better testability and improves reliability.
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机译：对更高带宽DRAM的需求不断增长，推动了TSV技术的发展。凭借小间距宽I / O [1]的能力，DRAM可以直接集成在插入器或主机芯片上，并与存储控制器进行通信。但是，在开发该技术时存在许多限制，例如可靠性和可测试性。在插入器和具有数千个TSV的堆叠式DRAM之间采用逻辑接口芯片是有利的。高带宽存储器（HBM）基本级别中的逻辑接口芯片降低了CIO，修复了芯片间的连接故障，并支持了更好的可测试性并提高了可靠性。
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