Increasing demand for higher-bandwidth DRAM drive TSV technology development. With the capacity of fine-pitch wide I/O [1], DRAM can be directly integrated on the interposer or host chip and communicate with the memory controller. However, there are many limitations, such as reliability and testability, in developing the technology. It is advantageous to adopt a logic-interface chip between the interposer and stacked-DRAM with thousands of TSV. The logic interface chip in the base level of high-bandwidth memory (HBM) decreases the CIO, repairs the chip-to-chip connection failure, and supports better testability and improves reliability.
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机译：增加对高带宽DRAM驱动器TSV技术开发的需求。具有细间距I / O [1]的容量，DRAM可以直接集成在插入器或主机芯片上并与存储器控制器通信。然而，在开发技术方面存在许多限制，例如可靠性和可测试性。采用插入器和堆叠的逻辑界面芯片具有数千个TSV是有利的。高带宽存储器（HBM）基本级别的逻辑接口芯片减少了CIO，修复芯片到芯片的连接故障，并支持更好的可测试性并提高可靠性。
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