Variation in process parameters results in an appalling number of SRAM failures which jeopardize design yield. These variations are expected to get further aggravate with technology scaling. Adaptive Body Bias (ABB) and Dynamic Voltage Scaling (DVS) are the useful techniques to alleviate the impact of process variation. However, with continued technology scaling, the achievable performance by ABB or DVS alone is becoming limited. In this paper, we propose a process corner based sensitivity-driven approach for self-restoring SRAM design by amalgamating ABB with DVS. More importantly, we leverage the contradiction between read-write stabilities and uneven conduct of inter-die process variation to Noise Margins (NMs) as a blessing of low-power SRAM design. Simulation results based on PTM 32nm CMOS technology quantify the viability and effectiveness of the scheme. Proposed approach meliorate Static Noise Margin (SNM), Read Noise Margin (RNM) and Write Margin (WM) by 12.6%, 59.2%and 6.1%, respectively. In addition, leakage current is reduced by 57.1% and a power redeem of 67.9%, 13.1% and 5.2% is achieved in hold, read and write mode, respectively.
展开▼
