A Bit Sampled Wake-Up Receiver with Logarithmic Detector Architecture

摘要

The bit sampled wake up receiver, providing both low sensitivity and low power consumption, is very competitive against other wake up receivers. In this paper, a bit sampled wake-up receiver with logarithmic detector architecture is presented. Theoretically, the proposed receiver has the lower sensitivity than tuned RF receiver of the same amplification gain, which majorly determines the overall power of the receiver. Also we conducted an experiment with the off the shelf circuit to measure the performance of the proposed receiver. According to our test, this receiver is able to give the scalable current consumption from 3.1μA to 146.5μA at the data rate from 10bps to 1kbps accordingly. The sensitivity of the circuit can reach - 77dBm regardless of data rate.