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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A 2.4 GHz Interferer-Resilient Wake-Up Receiver Using A Dual-IF Multi-Stage N-Path Architecture
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A 2.4 GHz Interferer-Resilient Wake-Up Receiver Using A Dual-IF Multi-Stage N-Path Architecture

机译:使用双IF多级N路径架构的2.4 GHz干扰器弹性唤醒接收器

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A 2.4 GHz interferer-resilient wake-up receiver for ultra-low power wireless sensor nodes uses an uncertain-IF dualconversion topology, combining a distributed multi-stage N-path filtering technique with an unlocked low-Q resonator-referred local oscillator. This structure provides narrow-band selectivity and strong immunity against interferers, while avoiding expensive external resonant components such as BAW resonators or crystals. The 65 nm CMOS receiver prototype provides a sensitivity of -97 dBm and a carrier-to-interferer ratio better than -27 dB at 5 MHz offset, for a data rate of 10 kb/s at a 10-3 bit error rate, while consuming 99 μW from a 0.5 V voltage supply under continuous operation.
机译:用于超低功率无线传感器节点的2.4 GHz干扰弹性唤醒接收器使用不确定IF双转换拓扑,将分布式多级N路径滤波技术与未锁定的低Q谐振器称为本地振荡器相结合。这种结构提供了窄带选择性和强大的抗干扰能力,同时避免了昂贵的外部谐振组件,例如BAW谐振器或晶体。 65 nm CMOS接收器原型在5 MHz偏移时提供-97 dBm的灵敏度和优于-27 dB的载波干扰比,在10-3比特误码率下的数据速率为10 kb / s,而在连续工作的情况下,从0.5 V电压电源消耗99μW的电流。

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