Reconfigurable Cell Architecture for Systolic and Pipelined Computing Datapaths

摘要

This paper introduces a recon??gurable computing cell architecture for pipelined and systolic datapaths in the Mixed Grained recon??gurable Coprocessor array system(MiGCop). The cell is efficiently capable of building scalable parallel-parallel, serial-parallel, and serial-serial signed multipliers. Several cells can be combined to form are con??gurable coprocessor that is tightly coupled with clusters of specially-designed lightweight RISC processors. In this paper, we present two different cell structures and com-pare their implementations using the 0.13um standard cell CMOS technology from Faraday and select the design with the most efficient area-delay product for the emerging MiGCop system. We will show that the cells are capable of computation frequencies higher than 250 MHz at a reason-able power consumption.