Higher circuit densities in System-on-a-Chip (SoC) designs have led to drastic increase in test data volume. Larger test data size demands not only higher memory requirements, but also an increase in testing time. In order to reduce the volume of SoC test data, an improved FDR code was proposed, called Variable Prefix Dual-Run-Length Code. This coding scheme has two steps: firstly, the don't care bits in the test data are filled with 0s or 1s using the Dynamic Programming Algorithm (DPA); then according to the novel partition way, the test data was divided as alternate runs of 0's and 1's, and the 0 runs and 1 runs was encoded. Due to its simple architecture, the decompression circuit for this proposed code needs only little additional hardware. Experimental results for the ISCAS'89 benchmark circuits show that the proposed code outperforms other similar codes in achieving higher compression ratio and requiring smaller area overhead for the on-chip decoder.
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