Digital-to-Time Converter with Pulse Train Generation Capability

摘要

A new field-programmable gate array (FPGA) based digital-to-time converter (DTC) is described that has a unique feature of pulse train generation with very high resolution. As a proof of concept the DTC design was implemented in Spartan-6 FPGA device (45 nm CMOS, Xilinx). The converter generates either absolute delay related to trigger signal or pulse sequence with variable relative delays between pulses. In both cases the resolution of delays is about 20 ps. The time interval between two pulses is generated with jitter below 4.5 ps. An important advantage of the design is also relatively easy implementation.