Error Rate Control through Dynamic Frequency Scaling for Minimum-Energy Point Operation in Razor-Based Processors

摘要

In an attempt to address the pressing concern for low-power operation, a Dynamic Voltage Scaling (DVS) technique in pipelined processors, Razor, was proposed in 2003 to minimize energy consumption by eliminating supply voltage margins. Razor introduced significant energy savings at a higher throughput despite the additional power and cycle count for error detection and correction. This work explores the use of Dynamic Frequency Scaling (DFS) instead of DVS for error rate control. To maximize the capabilities of Razor, model libraries for supply voltages of 0.2 V to 1.2 V were generated to characterize the ARM9 core. From the core timing properties, a supply voltage aware digitally programmable ring oscillator (SVADPRO) was designed to get different clock periods for DFS. Through the implementation of a dynamic frequency scaled Razor on an ARM9 core, energy consumption was reduced by up to 29% while maintaining the same throughput, compounded by a reduction in the energy-delay product by up to 10%.