Novel Low Power Noise Tolerant Dynamic Circuit Design Technique

摘要

To address the noise reliability issue in deep submicron digital circuits, a new noise-tolerant dynamic circuit technique has been proposed here. The main emphasis has been placed on reducing the power consumption of the circuit. The average noise threshold energy (ANTE) and the Energy normalized ANTE metrics have been used to quantify the noise immunity and power consumption improvement. A 2 input AND gate has been designed and simulated using 0.15 micron BSIM3V3.3 technology to indicate that the proposed technique improves the ANTE and Energy normalized ANTE by 7.14X and 4X over the conventional domino circuit. The improvement in the power consumption reduction is 33.3% higher than the existing noise-tolerance Mendoza Techniques.