Trax player implementation on FPGA using high level synthesis tool

摘要

In this paper, we describe our Trax player implemented on FPGA for FPT2016 design competition, which is designed by using a high-level synthesis tool, Xilinx Vivado HLS. The previous version of our design had recursive functions in the AI part, which could not be synthesized by Vivado HLS. They were processed by software using a hard IP processor. We rewrite them to non-recursive functions to synthesize using the HLS tool. The most part of our code becomes synthesizable in the current version.