This paper presents a multi-bit continuous-time ΔΣ modulator intended for ultra low power radios. The modulator features a 2nd order loop filter implemented with a single operational amplifier to reduce the power consumption. Furthermore, a 4-bit quantizer is used to achieve high resolution at a low oversampling ratio of 16. The ΔΣ modulator has been implemented in a 65nm CMOS process. Simulation results show a peak SNDR of 65 dB over a 500 kHz signal bandwidth, while consuming 76 μW from a 800 mV power supply.
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