首页> 外文会议>IEEE Custom Integrated Circuits Conference >A 16nm configurable pass-gate bit-cell register file for quantifying the VMIN advantage of PFET versus NFET pass-gate bit cells
【24h】

A 16nm configurable pass-gate bit-cell register file for quantifying the VMIN advantage of PFET versus NFET pass-gate bit cells

机译:用于量化PFET的V MIN 优势的16nm可配置的传代栅极位单元寄存器文件与NFET通道栅极位单元格

获取原文

摘要

A 16nm configurable pass-gate bit-cell register file allows a direct comparison of NFET versus PFET pass-gate bit cells for early technology evaluation. The configurable pass gate enables either a transmission-gate (TG), an NFET pass gate, or a PFET pass gate. From silicon test-chip measurement, the register file with PFET pass-gate bit cells achieves a 33% minimum supply voltage (V) reduction in a 16nm FinFET technology and a 40% V reduction in an enhanced 16nm FinFET technology as compared to a register file with NFET pass-gate bit cells. Test-chip measurements highlight the superior benefits of the PFET drive current relative to the NFET drive current at low voltages. The V improvement with a PFET pass-gate bit cell represents a paradigm-shift from traditional CMOS circuit-design practices.
机译:16NM可配置的传代栅极位单元寄存器文件允许直接比较NFET与PFET通道栅极位单元进行早期技术评估。可配置的传输门使得传输门(Tg),NFET通过门或PFET通过门。从硅测试芯片测量中,具有PFET通道栅极位单元的寄存器文件达到16nm FinFET技术的最小电源电压(v)减少,并且与寄存器相比,增强的16nm FinFET技术降低了40%V.带有NFET Pass-inal Bit单元的文件。测试芯片测量突出了PFET驱动电流相对于低电压下的NFET驱动电流的优越益处。使用PFET通道栅极位单元的V改进表示来自传统CMOS电路设计实践的范式转换。

著录项

相似文献

  • 外文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号