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A 16nm configurable pass-gate bit-cell register file for quantifying the VMIN advantage of PFET versus NFET pass-gate bit cells

机译:一个16nm可配置的传输门位单元寄存器文件,用于量化PFET与NFET传输门位单元的V MIN 优势

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A 16nm configurable pass-gate bit-cell register file allows a direct comparison of NFET versus PFET pass-gate bit cells for early technology evaluation. The configurable pass gate enables either a transmission-gate (TG), an NFET pass gate, or a PFET pass gate. From silicon test-chip measurement, the register file with PFET pass-gate bit cells achieves a 33% minimum supply voltage (V) reduction in a 16nm FinFET technology and a 40% V reduction in an enhanced 16nm FinFET technology as compared to a register file with NFET pass-gate bit cells. Test-chip measurements highlight the superior benefits of the PFET drive current relative to the NFET drive current at low voltages. The V improvement with a PFET pass-gate bit cell represents a paradigm-shift from traditional CMOS circuit-design practices.
机译:16nm可配置的传输门位单元寄存器文件允许直接比较NFET和PFET传输门位单元,以进行早期技术评估。可配置的传输门启用传输门(TG),NFET传输门或PFET传输门。从硅片测试芯片的测量来看,与寄存器相比,具有PFET传输门位单元的寄存器堆在16nm FinFET技术中实现了33%的最小电源电压(V)降低,在增强型16nm FinFET技术中实现了40%V的降低。带有NFET传输门位单元的文件。测试芯片的测量结果突出显示了PFET驱动电流相对于低电压下的NFET驱动电流的优越性。 PFET传输门位单元的V改善代表了传统CMOS电路设计实践的典范转变。

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