Design Considerations and Benefits of Three-Dimensional Ternary Content Addressable Memory

摘要

Three dimensional (3D) ternary content addressable memory (TCAM) has been designed in a 0.18μm fully depleted silicon on insulator (FD SOI) 3D IC process. This paper demonstrates that a 3D TCAM with three tiers can achieve 40% matchline capacitance reduction and 21% power reduction compared to a TCAM in a conventional single-tier process. This paper also discusses design considerations of 3D TCAM including partitioning methods for multiple tiers and layout methods of interconnects.