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Multi-Bit Sigma Delta ADC with Reduced Feedback Levels, Extended Dynamic Range and Increased Tolerance for Analog Imperfections

机译:多位Sigma Delta ADC具有降低的反馈水平,扩展动态范围和增加的模拟缺陷公差

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A novel second order sigma delta modulator (SDM) with 5-bit quantizer has been proposed with simplified DAC arrays, high-order truncation noise shaping for increased tolerance to analog imperfections, and extended dynamic range for a maximum input signal swing of up to -0.45dBFS. With truncation filter and pseudo SDM in the DSP, the truncation and saturation errors are compensated through the DAC arrays and the DSP. The design was fabricated in 0.18u Dual Gate Oxide (DGO) process. A SNDR (Signal-to-Noise-and驴Distortion Ratio) of 98.4 dB and a SNR (Signal-to-Noise Ratio) of 108-dB were measured for a 31.25-KHz signal bandwidth at 8-MHz sampling frequency with a power consumption of about 14.7 mW.
机译:具有5位量子化器的新型二阶Sigma Delta调制器(SDM),简化了DAC阵列,高阶截断噪声整形,用于增加对模拟缺陷的容差,并扩展动态范围,以获得最大的输入信号摆动 - 0.45dbfs。通过DSP中的截断滤波器和伪SDM,通过DAC阵列和DSP来补偿截断和饱和误差。该设计是在0.18U双栅氧化物(DGO)过程中的制造。以8-MHz采样频率为31.25-kHz信号带宽测量98.4dB的SNDR(信噪比和驴失真率)为98.4dB的98.4dB和SNR(信噪比),以8-MHz采样频率为电源消耗约14.7兆瓦。

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