Dynamic range extension technique for high-order /spl Sigma//spl Delta/ ADCs by digital level control

摘要

A new architecture is presented for a high-order multi-bit /spl Sigma//spl Delta/ ADC which does not require a precision multi-bit DAC in the feedback loop. Local digital level control is employed to extend integrator output dynamic range. A prototype fourth-order modulator is simulated with circuit non-idealities, showing an SNR of /spl sim/110 dB.