A 0.9V 45MS/s CT ΔΣ Modulator with 94dB SFDR and 25.6fJ/conv. enabled by a Digital Static and ISI Calibration in 22 FDSOI CMOS

摘要

State-of-the-art wideband continuous-time delta-sigma modulator (CT $Delta Sigma mathrm{M}$) architectures incorporate at least one multi-bit feedback DAC which intrinsically limits the $mathrm{CT} Delta Sigma mathrm{M}$ linearity. This paper proposes a $mathrm{CT} Delta Sigma mathrm{M}$ with background static and inter-symbol interference (ISI) calibration to achieve high linearity, a small area and leading edge power efficiency.