A 0.7 V 12b 160MS/S 12.8fJ/conv. Calibration-free Pipelined-SAR ADC in 28nm CMOS with Digital Amplifier Technique

摘要

We propose a calibration-free 0.7V 12b 160MS/s Pipelined-SAR ADC with digital amplifier (DA) technique [1]. DA cancels out all errors of the low-gain amplifier by feedback based on successive approximation (SA). Errors are detected by judging virtual ground polarity and canceled out by a C-DAC. The amplification accuracy is determined by the C-DAC LSB step and irrelevant to the intrinsic gain, and thus suitable for scaled CMOS. To further enhance the PVT tolerance of the ADC, look-ahead SAR and time-based current generation techniques are also introduced. The ADC is two-way interleaved and designed in 28nm CMOS. Without any calibration, SNDR of 61.1dB is achieved at Nyquist, consequently achieving FoM of 12.8fJ/conv. To the author's knowledge, this is over 3x improvement compared with the conventional calibration-free pipelined/pipelined-SAR ADCs with fs>50MS/s and SNDR>56dB.